Additional
Information: High Level Synthesis (or Behavioural Synthesis) is automatic compilation (translation) from a description which is relatively easy to write and read to a representation that can be automatically implemented. The most common synthesis today compiles from a
High Level Synthesis further on these related pages:
Visual Architect Visual Architect: Vendor description of an application-specific, high-level behavioral synthesis tool to assist in the development of SoC products. (High Level Synthesis) http://www.cadence.com/articles/visualArc.html
Integrated Embedded Systems Automation Group Integrated Embedded Systems Automation Group: Conducts design and design automation research projects including high level synthesis, reconfigurable designs and architectures and system modelling. Includes project descriptions, papers and tools. From University of California, Irvine. (High Level Synthesis) http://www.cecs.uci.edu/~iesag/
NEAT NEAT: Includes the infrastructure needed to build a HLS system including documentation, publications and tools. The commercial usage of the New Eindhoven Architectural Synthesis Toolkit sources and documentation are owned by a corporation. From Eindhoven Univer (High Level Synthesis) http://www.ics.ele.tue.nl/es/research/neat/
EDTN Links EDTN Links: Comprehensive list of links to information about commercial HLS tools. (High Level Synthesis) http://www.edtn.com/edatools/cae11.html
SPARCS Project SPARCS Project: Synthesis and Partitioning for Adaptive and Reconfigurable Computer Systems is an integrated design system for automatically partitioning and synthesizing designs for reconfigurable boards with multiple field-programmable devices (FPGAs). Includes overvie (High Level Synthesis) http://www.ececs.uc.edu/~ddel/projects/sparcs/sparcs.html
Daniel Gajski Daniel Gajski: Well known researcher. (High Level Synthesis) http://www.ics.uci.edu/~gajski/